Szamologep Project Status
Project File: Szamologep.ise Implementation State: Synthesized
Module Name: Calculator
  • Errors:
No Errors
Target Device: xc3s250e-4tq144
  • Warnings:
2 Warnings
Product Version:ISE 11.4
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 84 2448 3%
Number of Slice Flip Flops 33 4896 0%
Number of 4 input LUTs 149 4896 3%
Number of bonded IOBs 31 108 28%
Number of MULT18X18SIOs 1 12 8%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentK márc. 2 23:51:24 201002 Warnings0
Translation ReportOut of DateK márc. 2 10:03:10 2010000
Map ReportOut of DateK márc. 2 10:03:19 2010002 Infos
Place and Route ReportOut of DateK márc. 2 10:03:33 2010003 Infos
Power Report     
Post-PAR Static Timing ReportOut of DateK márc. 2 10:03:36 2010003 Infos
Bitgen ReportOut of DateK márc. 2 10:03:43 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateK márc. 2 22:36:07 2010

Date Generated: 03/10/2010 - 19:59:33